Integrated Circuits Comprising Patterned Functional Liquids

Field-effect gating with solid dielectrics is the basis for modern electronics. Electrolyte gating, however, offers far higher polarizations. Indeed, electrolyte gating has been a breakthrough to electrically induce numerous phase transitions in solids. These experiments are all done by dripping mm-size drops of the electrolytes onto the active sample. Compared to integrated circuit technology this approach seems outdated to us. These drops are open to the environment, and allow only for limited purity, reproducibility, and integration.

As reported in Advanced Materials, 1802598 (2018), we have achieved breakthrough to solve these problems. Heterostructure electronic circuits have, up to now, been comprised of solid materials only. We have opened this materials space to also include liquids. We demonstrate integrated liquid capacitors and integrated liquid field effect devices which are of equal quality or even outperform standard, bulk devices. This result will accelerate discoveries based on electrolyte gating by providing a new platform, and opens a new area to exploit liquid/solid interfaces in integrated functional devices with technological promise.

 

For more information see:
Advanced Materials, 1802598 (2018)

 

Fig 1: Sketch of envisioned solid-state/liquid-state heterostructures. This cross section illustrates the freedom of design and advances achievable if microscopic volumes of liquids (colored) were integrated into heterostructures. In the liquid volumes, for example, ions may create electric double layers (center) or move across gaps (sketch at right). Zoom Image
Fig 1: Sketch of envisioned solid-state/liquid-state heterostructures. This cross section illustrates the freedom of design and advances achievable if microscopic volumes of liquids (colored) were integrated into heterostructures. In the liquid volumes, for example, ions may create electric double layers (center) or move across gaps (sketch at right).

Fig 2: Illustration of a typical state-of-the-art sample setup used for ionic gating. A macroscopic drop of an electrolyte (blue) dropped onto the sample provides the gate liquid. Zoom Image
Fig 2: Illustration of a typical state-of-the-art sample setup used for ionic gating. A macroscopic drop of an electrolyte (blue) dropped onto the sample provides the gate liquid.

Fig 3: Sketch illustrating the vision of a sample containing integrated, microscopic liquid volumes, as opposed to Fig 2. Different liquids patterned into distinct shapes may be placed onto the sample at well-determined locations and then overgrown by subsequent layers. Zoom Image
Fig 3: Sketch illustrating the vision of a sample containing integrated, microscopic liquid volumes, as opposed to Fig 2. Different liquids patterned into distinct shapes may be placed onto the sample at well-determined locations and then overgrown by subsequent layers.

Fig 4: Optical microscopy image of a capacitor with integrated NaCl-H2O dielectric of ≈20 μm diameter (green arrow). Zoom Image
Fig 4: Optical microscopy image of a capacitor with integrated NaCl-H2O dielectric of ≈20 μm diameter (green arrow).


Fig 5: Photograph of a sample with 16 integrated capacitors after deposition of NaCl, before H2O deposition. The green arrows point to three of the capacitors (small bright dots). Zoom Image
Fig 5: Photograph of a sample with 16 integrated capacitors after deposition of NaCl, before H2O deposition. The green arrows point to three of the capacitors (small bright dots).
Fig 6: Top: Optical microscopy images of a ZnO-field-effect transistors with integrated NaCl-H2O dielectrics (arrow). These transistors have channel lenghts l≈10–20 μm. Bottom: Optical microscopy images of a chip containing 16 FETs. The FET of line 3, row 1 is shown in the top panel. Zoom Image
Fig 6: Top: Optical microscopy images of a ZnO-field-effect transistors with integrated NaCl-H2O dielectrics (arrow). These transistors have channel lenghts l≈10–20 μm.
Bottom: Optical microscopy images of a chip containing 16 FETs. The FET of line 3, row 1 is shown in the top panel.
 
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